module axiw_arbitor(
    input logic clk,
    input logic rst_n,
    //来自主机
    input logic m0_awvalid,
    input logic m1_awvalid,
    input logic m2_awvalid,
    input logic m3_awvalid,
    //来自从机
    input logic m0_bvalid,
    input logic m1_bvalid,
    input logic m2_bvalid,
    input logic m3_bvalid,
    //来自主机
    input logic m0_bready,
    input logic m1_bready,
    input logic m2_bready,
    input logic m3_bready,
    //
    output logic [2:0] cur_master           //0表示当前总线被主机0占用,以此类推
);

typedef enum bit [2:0] {
    IDLE,
    MASTER0,                        //主机0占用总线
    MASTER1,                        //主机1占用总线
    MASTER2,                        //主机2占用总线
    MASTER3                         //主机3占用总线
} State;
//
logic [3:0] master_req;
logic end0;
logic end1;
logic end2;
logic end3;
State state,next_state;
//
assign master_req={m3_awvalid,m2_awvalid,m1_awvalid,m0_awvalid};
//
always_ff@(posedge clk,negedge rst_n)
if(~rst_n)
    state<=IDLE;
else 
    state<=next_state;
//
always_comb
begin
    case(state)
	       IDLE:if(~rst_n)
	                next_state=IDLE;
				else if(master_req[0])
				    next_state=MASTER0;
				else if(master_req[1])
				    next_state=MASTER1;
				else if(master_req[2])
				    next_state=MASTER2;
				else if(master_req[3])
				    next_state=MASTER3;
				else 
				    next_state=IDLE;
		  MASTER0:if((m0_bvalid&&m0_bready)||end0)
		             if(master_req[1]) next_state=MASTER1;
					 else if(master_req[2]) next_state=MASTER2;
					 else if(master_req[3]) next_state=MASTER3;
					 else if(master_req[0]) next_state=MASTER0;
				     else next_state=MASTER0;
				  else
				     next_state=MASTER0;
		  MASTER1:if((m1_bvalid&&m1_bready)||end1)
		             if(master_req[2]) next_state=MASTER2;
					 else if(master_req[3]) next_state=MASTER3;
					 else if(master_req[0]) next_state=MASTER0;
					 else if(master_req[1]) next_state=MASTER1;
					 else next_state=MASTER1;
				  else 
				     next_state=MASTER1;
		  MASTER2:if((m2_bready&&m2_bvalid)||end2)
				     if(master_req[3]) next_state=MASTER3;
				     else if(master_req[0]) next_state=MASTER0;
					 else if(master_req[1]) next_state=MASTER1;
					 else if(master_req[2]) next_state=MASTER2;
					 else next_state=MASTER2;
		  MASTER3:if((m3_bready&&m3_bvalid)||end3)
                     if(master_req[0]) next_state=MASTER0;
					 else if(master_req[1]) next_state=MASTER1;
					 else if(master_req[2]) next_state=MASTER2;
					 else if(master_req[3]) next_state=MASTER3;
					 else next_state=MASTER3;
		  default:next_state=IDLE;
	endcase
end
//end0,1,2,3
always_ff@(posedge clk,negedge rst_n)
if(~rst_n)
begin
    end0<=0;
	end1<=0;
	end2<=0;
	end3<=0;
end
else
case(state)
    IDLE:{end3,end2,end1,end0}<=4'b0000;
	MASTER0:if(m0_bready&&m0_bvalid&&(|master_req==1'b0))   
	            end0<=1;
	        else if(|master_req&&end0)                       //处理下一次请求
			    end0<=0;
	MASTER1:if(m1_bready&&m1_bvalid&&(|master_req==1'b0))
	            end1<=1;
			else if(|master_req&&end1)
			    end1<=0;
	MASTER2:if(m2_bready&&m2_bvalid&&(|master_req==1'b0))
	            end2<=1;
			else if(|master_req&&end2)
			    end2<=0;
	MASTER3:if(m3_bready&&m3_bvalid&&(|master_req==1'b0))
	             end3<=1;
			else if(|master_req&&end3)
			     end3<=0;
	default:;
endcase
//
always_comb
case(state)
    IDLE:cur_master=0;
    MASTER0:cur_master=0;
    MASTER1:cur_master=1;
    MASTER2:cur_master=2;
    MASTER3:cur_master=3;
    default:cur_master=0;
endcase	
endmodule

